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fedl9480-01 issue date: oct. 1, 2012 ML9480 static, 1/2 duty, 1/3 duty, 1/4 duty 40 outputs lcd driver 1/37 general description the ML9480 is an lcd driver lsi, consists of a 40-bit shift register, a 160-bit data latch, 40 sets of lcd drivers, and a common signal generation circuit. it can directly drive an lcd up to 40 segments for static display, 80 segments for 1/2-duty display, 120 segments for 1/3-duty display, and 160 segments for 1/4-duty display. the three-wire serial interface and i 2 c interface are selectable. features ? ? logic power supply voltage : 2.7 to 5.5 v ? lcd drive power supply voltage : 4.5 to 5.5 v ? maximum number of segments static display : 40 segments 1/2-duty display : 80 segments 1/3-duty display : 120 segments 1/4-duty display : 160 segments ? interface with microcomputer : serial interface : data, clock, load clock transfer speed up to 1 mhz i 2 c interface : sda, scl, sdaack scl transfer speed up to 400 khz ? built-in cr oscillator circuit using the internal resistor or external resistor ? cascade connectable (up to sixteen chips) ? built-in common signal generation circuit ? built-in common output intermediate-value voltage generation circuit ? built-in poc (power on clear) circuit ? gold bump chip (ML9480dvwa)
fedl9480-01 ML9480 2/37 block diagram 40-dot segment driver latch selector load osc latch1 latch2 dat a sd a clock scl bias vdd gnd timing generator 40-ch data selector common driver seg1 seg40 com1 40-bit shift register 40-bit 40-bit 40 com2 com3 com4 duty0 40 40 40 40 vlcd bias resi. osc i/e oscr osc1 osc2 duty1 latch4 40-bit 40-bit latch3 resetb command decoder sdaack sa1 a1 a0 cko syncb m/s poc circuit i2c test1 poceb sa0 mode
fedl9480-01 ML9480 3/37 absolute maximum ratings item symbol condition rating unit logic power supply voltage v dd ta = 25c -0.3 to 6.0 v lcd drive power supply voltage v lcd ta = 25c - 0.3 to 6.0 v input voltage v i ta = 25c ? 0.3 to v dd + 0.3 v output short-circuit current is ta = 25c - 2.0 to +2.0 ma chip temperature tc ? 125 c storage temperature t stg ? -55 to +150 c note: do not use the ML9480 by short-circuiting one output pin to another output pin as well as to other pin (input pin, input/output pin, or power supply pin). recommended operation conditions item symbol condition range unit logic power supply voltage v dd * ? 2.7 to 5.5 v lcd drive power supply voltage v lcd * ? 4.5 to 5.5 v osc in clock frequency f cp1 ? up to 10 khz data clock frequency f cp2 ? up to 1.0 mhz scl clock frequency f scl ? up to 400 khz operating temperature t a ? -40 to +105 c note(*): use at v dd ? v lcd . the relation between osc in clock frequency and frame frequency is as the equation below. f frm = f osc /24 recommended setting range for external component (oscillator circuit) (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= ?40 to +105c) item symbol condition min typ max unit oscillation resistor r f ? 423 470 517 k ? frame frequency f frm (f1,f0)=(0,1) 47 75 114 hz the relation between oscillation resistor and frame frequency is as the equation below. f frm = f osc /(16 x 24) fosc = 1 / (device coefficient x external resistor r f ) device coefficient = 73.8 x 10 -12 25%
fedl9480-01 ML9480 4/37 electrical characteristics dc characteristics (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= -40 to +105c) item symbol condition min. typ. max. unit applicable pin "h" input voltage v ih ? 0.8v dd ? v dd v (*1) "l" input voltage v il ? gnd ? 0.2v dd v (*1) input leakage current 1 i l1 v i = v dd or 0 v -1.0 ? 1.0 ? a (*1) input leakage current 2 i l2 v i = v dd or 0v poceb="h" -1.0 ? 1.0 ? a resetb pull-up current i pu v dd = 5.0v,v i = 0 v poceb = "l" 30 ? 140 ? a resetb "h" output voltage v oh i o = -600ua 0.9v dd ? ? v ? cko, syncb "l" output voltage 1 v ol1 i o = 600ua ? ? 0.1v dd v cko, syncb "l" output voltage 2 v ol2 vdd=5v, v ol = 0.4v 3 ? ? ma sdaack segment v ohs v lcd = 5v ? 5 15 k ? seg1 to seg40 driver on resistor common v ohc v lcd = 5v ? 5 12 k ? com 1 to com4 (*1) : data(sda), clock(scl), load, m/s, syncb, duty1, duty0, bias, sa1,sa0, a1, a0, osc1, osc i/e, i2c, poceb, mode (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= -40 to +105c) item symbol condition min. typ. max. unit applicable pin i dds ? 8 15 ? a vdd static supply current i lcds v dd =v lcd =5.5 v input pin fixed to "h" or "l" oscillation stopped, output no-load poceb="l" ? 9 15 ? a vlcd i dd1 (*6) ? 10 18 ? a vdd dynamic supply current 1 i lcd1 v dd =v lcd = 5.5 v (*2)(*3) clock osc1 external input f cp1 =1.8khz (*7) ? 9 13 ? a vlcd i dd2 (*6) ? 59 90 ? a vdd dynamic supply current 2 i lcd2 v dd =v lcd = 5.5 v (*2)(*3) internal oscillation (*7) ? 9 15 ? a vlcd i dd3 ? 100 200 ? a vdd dynamic supply current 3 i lcd3 v dd =v lcd = 5.5 v (*2)(*4)(*6) internal oscillation at three-wire serial if data input ? 9 15 ? a vlcd i dd4 ? 188 310 ? a vdd dynamic supply current 4 i lcd4 v dd =v lcd = 5.5 v (*2)(*5)(*6) internal oscillation at i 2 c if data input ? 9 15 ? a vlcd (*2) : m/s = "h", 1/4-duty, 1/3-bias, (f1,f0,fsel) = (1,1,0) 95 hz, poceb = "l", output pin no-load. (*3) : three-wire serial or i 2 c interface. input pin fixed to "h" or "l". (*4) : serial interface, data input frequency = 1 mhz. (*5) : i 2 c interface, data input frequency = 400 khz. (*6) : alternately inputs "0" and "1" for lcd display data (checkered display). (*7) : inputs all "1s" for lcd display data (all illuminated).
fedl9480-01 ML9480 5/37 switching characteristics ? osc ti ming (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin osc in clock frequency (external input) f cp1 ? 1.8 10 khz osc1 clock pulse width (external input) t wcp1 40 ? ? ? s osc1 clock rise and fall time (external input) t osc clock input from osc1. osc2 and oscr open. osc i/e = "l" ? ? (*1) ? s osc1 external rf clock frequency (internal oscillation) f osc1 between osc1 and osc2 r f = 470k ? (f1,f0)=(0,1) oscr open. osc i/e = "h" 18 28.8 44 khz osc1, osc2 internal clock frequency (internal oscillation) f osc2 osc1 open. (f1,f0)=(0,1) osc2 and oscr short-circuited. osc i/e = "h" 18 28.8 44 khz osc1, oscr, osc2 the relation between osc in clock frequency and frame frequency is as the equation below. f frm = f osc /24 (*1) t osc is a reference value. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=2 ? s. ? serial interface timing (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin data clock frequency f cp2 ? ? 1 mhz clock data clock pulse width t wcp2 100 ? ? ns clock data setup time t su 50 ? ? ns data data hold time t hd 50 ? ? ns clock clock-load timing t cl 100 ? ? ns clock load-clock timing t lc 100 ? ? ns load load pulse width t wld 100 ? ? ns load signal rise and fall time tsr,tsf ? ? (*2) ns ? clock,data, load (*2) tsr and tsf shall be reference values. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=10ns.
fedl9480-01 ML9480 6/37 ? i 2 c interface timing (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin scl clock frequency f scl ? ? 400 khz scl hold time (repeat) "statrt" condition t hd,sta 0.6 ? ? ? s scl,sda scl "l" pulse width t low 1.3 ? ? ? s scl scl "h" pulse width t high 0.6 ? ? ? s scl setup time for repeat "start" condition t su,sta 0.6 ? ? ? s scl,sda data hold time t hd,dat 0 ? ? ns scl,sda data setup time t su,dat 100 ? ? ns scl,sda setup time for "stop" condition t su,sto 0.6 ? ? ? s scl,sda bus free time between "stop" condition and "start" condition t buf 1.3 ? ? ? s scl data valid acknowledge time t vd,ack ? ? 1.2 ? s scl,sdaaack signal rise and fall time tir,tif ? ? (*3) ? s ? scl,sda data bus load capacitance cb ? ? 400 pf sda,sdaack noise pulse width tolerance t wf ? ? 50 ns scl,sda (*3) tir and tif shall be reference values. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=0.1 ? s.
fedl9480-01 ML9480 7/37 timing chart (osc1) osc1 (external clock) 1/f cp1 t wcp1 t wcp1 v ih v ih v il v il v ih t os c timing chart (serial interface) v ih v il v ih v il data clock v ih v ih v il v il v il v il load v ih v ih v il v il t wcp2 t wcp2 t hd t su 1/f cp2 t cl t lc t wld v ih v il t sf v ih v il t sr v ih t sr v ih v il t sf t sf t sr timing chart (i 2 c interface) t buf t low t vd;ack t r t f t hd;sta t hd;dat t high t su;dat t su;sto t su;sta sda scl sda v ih v il v ih v ih v il v ih v il v ih v ih v ih v ih v ih v il v il v il v il v il v ih v il
fedl9480-01 ML9480 8/37 reference data frame frequency characteristics vdd=5.5v/2.7v rf=470 ? frame frequency f frm = f osc /(16 x 24) fosc = 1 / (device coefficient x external resistor r f ) device coefficient = 73.8 x 10 -12 25% frame frequency characteristics rf=470k,vdd=5.5v 50 60 70 80 90 100 110 120 -60 -40 -20 0 20 40 60 80 100 120 temp ta[] frame frequency ffrm[hz] (f1,f0)=(1,1) (f1,f0)=(1,0) (f1,f0)=(0,1) (f1,f0)=(0,0) frame frequency characteristics rf=470k,vdd=2.7v 50 60 70 80 90 100 110 120 130 -60 -40 -20 0 20 40 60 80 100 120 tempta[] frame frequency ffrm[hz] (f1,f0)=(1,1) (f1,f0)=(1,0) (f1,f0)=(0,1) (f1,f0)=(0,0)
fedl9480-01 ML9480 9/37 power on/off timing to turn on the power supply, raise the logic power supply first, then lcd drive power supply in order to prevent the ic from malfunctioning. to fall the power supply, fall the lcd drive power supply first, then the logic power supply. for a vdd pin ranging from 0 v to vddmin, set vdd vlcd and t1 0 [ns]. to enable the internal poc circuit, the vdd power supply rise time t2 range needs to be 100 [s] ?? t2 ?? 500 [ms]. for the vdd power supply to turn off then turn on again, it is necessary to secure the poc discharge time t3 ?? 100 [ms]. initialization signal timing when resetb signal is externally input the resetb pin input is valid both for poceb = "l" and "h". usable in combination with the poc. keep the resetb pin at "l" level until the vdd reaches vddmin. (t4 200[ns]) when internal poc circuit is used w hen using the internal poc circuit in the initialization, set the poceb pin to "l". at this time, the power on/off timing conditions are t1 to t3 above mentioned. when resetb pin poc circuit is used if the power on/off timing conditions t1 to t3 cannot be kept, the resetb pin needs to have a capacitance to configure the poc circuit. for this case, connect a capacitance value according to the power supply rise time. for the power supply rise time t2 and external capacitance value, use the following formula as a guide: c rst [f] > t2 [sec] (30 10 3 ) v dd v lcd time voltage t1 t1 0.9v dd t2 v dd t3 v dd resetb vil t4 v dd min
fedl9480-01 ML9480 10/37 pin descriptions pad number symbol i/o description 32 m/s i this is the input to switch between the master and slave modes. it has a schmitt circuit. when this pin is "h", the mode is master. when this pin is "l", the mode is slave. 3,4 duty0 duty1 *1 i display duty switch pins. these have schmitt circuits. duty0="l", duty1="l" : static (com1=com2=com3=com4) duty0="h", duty1="l" : 1/2duty (com1=com3, com2=com4) duty0="l", duty1="h" : 1/3duty (com2=com4) duty0="h", duty1="h" : 1/4duty 35 bias i this pin sets the lcd bias. it has a schmitt circuit. bias="l": 1/3bias bias="h": 1/2bias when the static mode selection, fix this pin at ?h? or ?l? level. 7,8 sa1 sa0 i slave address input pins. these have schmitt circuits. 5,6 a1 a0 i sub address input pins. these have schmitt circuits. 34 osc i/e i this input selects whether to use the external clock input mode or to use the internal oscillation mode or external oscillation mode. it has a schmitt circuit. when this pin is "h", the mode is the internal or external rf oscillation mode. when this pin is "l", the mode is the external clock input mode. use the slave chip as it is connected to gnd. 24 to 26 osc1, oscr, osc2 *2 i i o these pins are for the oscillator circuit to generate common signals. the osc1 and oscr pins are input pins and have a schmitt circuit. osc2 is an output pin. it becomes an output when the osc i/e pin = "h" and a high impedance when the osc i/e pin = "l". in the master mode (m/s pin ="h") three types are selectable: internal oscillation mode, external oscillation mode, and external clock input mode. ?internal oscillation mode: set the osc i/e pin to "h", short the oscr and osc2 pins, and open the osc1 pin. ?external rf oscillation mode: set the osc i/e pin to "h", connect an oscillation resistor rf between the osc1 and osc2 pins, and open the oscr pin. ?external clock input mode: set the osc i/e pin to "l", open the oscr and osc2 pins, and input the external clock to the osc1 pin. in the slave mode (m/s pin ="l") open the oscr and osc2 pins and connect the osc1 pin to the ML9480's cko pin that has been set to the master mode. 27 cko o clock output pin. in the master mode (m/s pin = "h", fsel=?0?), the 1/16 division signal of the oscillation frequency is output. in the master mode (m/s pin = "h", fsel=?1?), the 1/8 division signal of the oscillation frequency is output. in the slave mode (m/s pin = "l"), the output is fixed to "l". for a cascade connection, connect this pin to the osc1 pin of the chip that has been set to the slave mode.
fedl9480-01 ML9480 11/37 28 syncb i/o input/output pin for common synchronization. it has a schmitt circuit. it becomes the synchronization signal output pin in the master mode (m/s pin = "h"). it becomes the synchronization signal input pin in the slave mode (m/s pin = "l"). for cascade connection, connect all of the involved ML9480s' sync pins by the common line. 30 i2c i interface switching pin. it has a schmitt circuit. when this pin is "h", the interface is i 2 c. when this pin is "l", the interface is three-wire serial. 11 data (sda) i display data input pin. it has a schmitt circuit. i2c="l": serial interface; data input the display data in the order of seg40, seg39, ... , seg2, and seg1. the display data turns on at "h" and turns off at "l". i2c="h": i 2 c interface; sda input the display data in units of 8 bits. the display data turns on at "h" and turns off at "l". this pin has a built-in noise filter through which noises in widths up to 50 ns are removed. this noise filter is valid only when i2c = "h". 12 clock (scl) i shift clock input pin for display data. it has a schmitt circuit. i2c="l": serial interface; clock the display data input to the data pin is serially input to the shift register at the clock signal rise. i2c="h": i 2 c interface; scl the display data input to the sda pin is serially input to the shift register at the scl signal rise. this pin has a built-in noise filter through which noises in widths up to 50 ns are removed. this noise filter is valid only when i2c = "h". 13 load i input pin for the load signal of display data. it has a schmitt circuit. i2c="l": serial interface; load the display data in the shift register is transmitted as is to the segment driver for the "h" duration. when this pin is brought into "l", the shift register is disconnected from the segment driver. the display data in the shift register immediately before it become "l" is held in the data latch and transmitted to the segment driver. i2c="h": i 2 c interface use this pin as it is connected to gnd. 10 sdaack o i2c="l": serial interface use this pin as it is opened. i2c="h": i 2 c interface the i 2 c bus acknowledge output signal. normally, use it as it is connected with the sda pin. connect an external pull-up resistor whenever necessary, as it is an open drain pin. the pull-up connection destination supply voltage shall be the v dd supply voltage or less. 33 poceb i internal poc circuit enable pin. it has a schmitt circuit. when this pin is "h", the poc circuit becomes off and the constant current (8a) is cut. the resetb pin pull-up resistor is cut as well. when this pin is "l", the poc circuit becomes on. the resetb pin is connected to a pull-up resistor. 23 resetb *3 i reset signal input pin for initializing inside the ic. it has a schmitt circuit. the "l" level enables the reset. this pin has an internal pull-up resistor. open when poceb = "h". pull-up when poceb = "l". the power-on reset operation is available by connecting an external capacitor.
fedl9480-01 ML9480 12/37 31 mode i i2c interface command table switching pin. it has a schmitt circuit. this pin is valid only when i2c = "h". when this pin is "l", the command table is table a. when this pin is "h", the command table is table b. when the three-wire serial interface mode selection, fix this pin at ?h? or ?l? level. 36 test1 i pin for testing the ic. it has a internal pull-down resistor. use it as it is connected to gnd. 45 to 64, 69 to 88 seg1 ? seg40 o outputs for lcd display. connected to the segment pins on the lcd panel. in the display off mode, all the outputs are fixed to gnd. 40 to 43, 65 to 68, 90 to 93 com1 ? com4 o outputs for lcd display. connected to the common pins on the lcd panel. the output pins are located at three positions: center and both ends of the chip. each is connected inside the chip. use the com pins in accordance with the panel to be used. in the display off mode, all the outputs are fixed to gnd. when the slave is set (m/s=?l?), com1 to com4 outputs are gnd level fixed. 14 to 16 vdd - power supply pin for logic circuit. 20 to 22 vlcd - power supply pin for lcd driver. 17 to 19 gnd - ground pin. 9,29 vddo - vdd output pin. use this pin when fixing the mode setting input pin to "h" on the cog. 2,37 gndo - ground output pin. use this pin when fixing the mode setting input pin to "l" on the cog. 1,38, 39,44, 89,94 dummy - floating pin. at this time, avoid this pin from shorting with pins other than dummy in the wiring on the cog. *1: for details of the com /seg waveform when a duty is selected, refer to "common waveform" on page 24 and "common segment waveform" on page 25 to 29. *2: oscillator circuit configuration ? when m/s = "h", osc i/e = "h" [internal rf oscillation mode] [external rf oscillation mode] open osc2 osc1 oscr osc2 r osc1 open oscr
fedl9480-01 ML9480 13/37 ? external clock input mode when m/s = "h" and osc i/e = "l" ? m/s = "l", slave mode, external clock input mode *3: reset circuit configuration ? external input to restb when poceb = "h" resetb vdd external input ? poc circuit configuration when poceb = "l" resetb vdd c rst osc2 osc1 open oscr open external clock osc2 osc1 op en oscr op en master cko
fedl9480-01 ML9480 14/37 description operation description (seria l interface) ? display data input as described in the data configuration section, the displa y data consists of the data field that corresponds to each segment on/off and the command field that indicates the display data input. when inputting the display data, the "f3" command is set in the command field. when the "f1" or "f2" command is set in the command field, the display data in the data field becomes invalid. the data input to the data pin is loaded to the shift register at the clock pulse rise, transferred to the display data latch during the load pulse at the "h" level, then output via the segment driver. d1 d2 d3 d4 d4 0 c0 c1 c2 c3 c4 c5 c6 clock data new data load display output c7 data field old data command field ? display on, display off the display becomes off at power-on reset. to display, write the display on command. the display off is the command that makes all segments off. writing the display off command turns off the lights regardless of the display data. the display on is the command to release the display off. writing the display on command returns the display to the original state. d1 d2 c6 c4 c5 c6 c7 c4 c5 c6 c7 clock data load display on/off c7 reset display data input display on command write display off command write
fedl9480-01 ML9480 15/37 list of commands t he ML9480 have two type command table. command table can be selected by i2c and mode input pins. i2c pin mode pin i/f command l * serial command table a h l i2c command table a h h i2c command table b list of command table a serial interface and i2c interface (when mode pin is "l") command name c7 c6 c5 c4 c3 c2 c1 c0 operation f0 0 0 x x x x x x disabled f1 0 1 f1 (*2) f0 (*2) fsel (*2) x x x frame frequency setting (valid for internal cr oscillation) when fsel =?0? (f1,f0)=(0, 0): 65hz (f1,f0)=(0, 1): 75hz (f1,f0)=(1, 0): 85hz (f1,f0)=(1, 1): 95hz when fsel = ?1? (f1,f0)=(0, 0): 130hz (f1,f0)=(0, 1): 150hz (f1,f0)=(1, 0): 170hz (f1,f0)=(1, 1): 190hz f2 1 0 1 d (*2) x x x x display on/off "0" : off com=seg=gnd "1" : on f3(*1) 1 1 sa1 sa0 a1 a0 co1 co0 data write address setting (co1,co0)=(0, 0): corresponding to common 1 (co1,co0)=(0, 1): corresponding to common 2 (co1,co0)=(1, 0): corresponding to common 3 (co1,co0)=(1, 1): corresponding to common 4 sa1, sa0, a1, a0: chip address x: don't care (*1): for the i 2 c interface, sa1 and sa0 are set at a slave address. these bits become "don't care". (*2): the register is set to the following value by the resetb = "l" input or by the power-on poc. f1="0", f0="0", fsel="0", d="0"
fedl9480-01 ML9480 16/37 list of command table b i 2 c interface(when mode pin is "h") operation code command name c7 c6 c5 c4 c3 c2 c1 c0 initialize mode set c 1 0 x d b m1 m0 d=b=m1=m2=?0? display ram address c 0 p5 p4 p3 p2 p1 p0 chip address c 1 1 0 0 a2 a1 a0 frame frequency select c 1 1 0 1 f1 f0 fsel f1=fsel=?0? f0=?1? bank select c 1 1 1 1 0 i o i=o=?0? blink select c 1 1 1 0 ab bf1 bf0 ab=bf1=bf0=?0? x: don't care c: continue bit 0:last control byte in the transfer 1:control byte continue mode set c7 c6 c5 c4 c3 c2 c1 c0 mode set c 1 0 x d b m1 m0 d: display on/off ?0?: off (com=seg=gnd) ?1?: on b: lcd bias setting ?0?: 1/3 bias ?1?: 1/2 bias this command becomes effective at i2c pin =?h? and mode pin=?h?. m[1:0]: duty setting m[1:0]=(0, 1) : static m[1:0]=(1, 0) : 1/2duty m[1:0]=(1, 1) : 1/3duty m[1:0]=(0, 0) : 1/4duty this command becomes effective at i2c pin =?h? and mode pin=?h?. display ram address c7 c6 c5 c4 c3 c2 c1 c0 display ram address c 0 p5 p4 p3 p2 p1 p0 p[5:0]=00_0000 to 10_0111 the increment of the display ram address is carried out automatically. static +8, 1/2duty +4, 1/3duty +3, 1/4duty +2
fedl9480-01 ML9480 17/37 chip address c7 c6 c5 c4 c3 c2 c1 c0 display ram address c 1 1 0 0 a2 a1 a0 a[2:0] = 111 to 000 the terminal corresponding to a2 is sa1 pin. the terminal corresponding to a1 is a1 pin. the terminal corresponding to a0 is a0 pin. frame frequency select c7 c6 c5 c4 c3 c2 c1 c0 frame frequency c 1 1 0 1 f1 f0 fsel frame frequency setting. this command becomes effective at i2c pin =?h?, mode pin=?h?, bias pin =?l? and internal cr oscillation. when bias pin =?h? and internal cr oscillation, frame frequency is set to 75hz (initialize). when fsel =?0? (f1,f0)=(0, 0): 65hz (f1,f0)=(0, 1): 75hz (f1,f0)=(1, 0): 85hz (f1,f0)=(1, 1): 95hz when fsel = ?1? (f1,f0)=(0, 0): 130hz (f1,f0)=(0, 1): 150hz (f1,f0)=(1, 0): 170hz (f1,f0)=(1, 1): 190hz bank select c7 c6 c5 c4 c3 c2 c1 c0 bank select c 1 1 1 1 0 i o i: input bank selection i static 1/2duty 0 com1 com1 & com2 1 com3 com3 & com4 this command has no effect in 1/3duty and 1/4duty mode. o: output bank selection o static 1/2duty 0 com1 com1 & com2 1 com3 com3 & com4 this command has no effect in 1/3duty and 1/4duty mode.
fedl9480-01 ML9480 18/37 blink select c7 c6 c5 c4 c3 c2 c1 c0 blink select c 1 1 1 0 ab bf1 bf0 ab: blink mode selection ?0?: normal blinking ?1?: alternate ram blinking does not apply in 1/3duty and 1/4duty. bf[1:0]: blink frequency selection bf1 bf0 blink frequency 0 0 blink off 65hz/130hz 75hz/150hz 85hz/170hz 95hz/190hz 0 1 2.03hz 2.34hz 2.66hz 2.97hz 1 0 1.01hz 1.17hz 1.33hz 1.48hz 1 1 0.51hz 0.59hz 0.66hz 0.74hz display data ram this is the ram storing the data of display and has an organization of 40 x 4. display ram data ram address map display ram data ?1? ... dot is displayed display ram data ?0? ... dot is not displayed display data ram address map seg 1 seg 2 seg 3 seg 4 seg 5 seg 37 seg 38 seg 39 seg 40 com1 ??? com2 ??? com3 ??? com4 ??? static drive ... com1 1/2duty drive ... com1, com2 1/3duty drive ... com1, com2, com3 1/4duty drive ... com1, com2, com3, com4 cascade connection when command table b is chosen (i2c pin =?h?, mode pin =?h?), ML9480 cannot used cascade connection.
fedl9480-01 ML9480 19/37 data configuration ? data configuration (serial interface) d40 d39 d38 d3 d2 d1 c0c1c2 c3 c4 c5 command lcd display data corresponding to seg1 corresponding to seg40 first bit c6 c7 note 1 : the commands f1 and f2 settings become valid when the least four bits of c4 to c7 are input. (the bits from d1 to d40 and from c0 to c3 are not necessary.) note 2 : if the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side. note 3 : the command execution follows the contents of the c7 to c0 registers immediately before the load becomes "h".
fedl9480-01 ML9480 20/37 ? data configuration (i 2 c interface, when mode pin is "l") for the i 2 c interface, each ic is assigned with a 7-bit slave address. the first one byte in the transfer consists of this 7-bit slave address and the r/w bit that indicates the data transfer direction. always input "0" to the eighth r/w bit because the ML9480 is a write-only lsi. the eight bits next to the slave address is a control byte. the first one bit is co: consecutive command setting bit and the next one bit is rs: command/data setting bit (the remaining six bits are the don't care bits). when co = "0": means the last control byte. when co = "1": means the control bytes are successively input. when rs = "0": means the data to be input next is the command data. when rs = "1": means the data to be input next is the display data. the display data can be successively input. example of data setting ? when inputting two commands ? when inputting the command and display data r/w s 01 100 sa1 sa0 0 a co rs a msb lsb p salve address: 0 1 1 0 0 1 co: consecutive control byte setting bit 0: last control b y te , 1: consecutive control b y te rs: command/data settin g bi t 0: command data, 1: display data slave address control byte data/command when inputting two commands s 01 100 sa1 sa0 0 a 10 aa 00 aa p command command s 01 100 sa1 sa0 0 a 10 aa 01 aaa aaap display data display data command display data display data
fedl9480-01 ML9480 21/37 ? data configuration (i 2 c interface, when mode pin is "h") r/w s 011100 sa0 0 a c a msb lsb ap salve address: 0 1 1 1 0 0 cconsecutive control byte setting bit 0last control b y te, 1consecutive control b y te slave address command display data for the i 2 c interface, each ic is assigned with a 7-bit slave address. the first one byte in the transfer consists of this 7-bit slave address and the r/w bit that indicates the data transfer direction. always input "0" to the eighth r/w bit because the ML9480 is a write-only lsi. the eight bits next to the slave address is a control by te. the first one bit is co: consecutive command setting bit. when co = "0": means the last control byte. when co = "1": means the control bytes are successively input. data write method ? serial interface the data is written to the address set by the data write setting command (f3). for the serial interface, the data is written in units of 40 bits. written from d40 to seg1, d39 to seg2, ... , d2 to seg39, and d1 to seg40. msb se g ment out p ut lsb 1 2 3 4 32 33 34 35 36 37 38 39 40 com1 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 com2 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 com3 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 com4 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 ? i 2 c interface (when mode pin is "l") the data is written to the address set by the slave address. for the i 2 c interface (when mode pin is "l"), the data is written to the specified address starting with the lsb side in units of 8 bits. (the data is written in the order from seg33-40, seg25-seg32, seg17-seg24, seg9-seg16, and seg1-seg8.) lsb se g ment out p ut msb 1234 323334353637383940 com1 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com2 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com3 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com4 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8
fedl9480-01 ML9480 22/37 ? i 2 c interface (when mode pin is "h") the data is written to the address set by the display ram address. for the i 2 c interface (when mode pin is "h"), the data is written to the specified address starting with the lsb side in units of 8 bits. static lsb se g ment out p ut msb 123456789 37383940 com1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d4 d3 d2 d1 com2 xxxxxxxxx xxxx com3 xxxxxxxxx xxxx com4 xxxxxxxxx xxxx 1/2duty lsb se g ment out p ut msb 123456789 37383940 com1 d8 d6 d4 d2 d8 d6 d4 d2 d8 d8 d6 d4 d2 com2 d7 d5 d3 d1 d7 d5 d3 d1 d7 d7 d5 d3 d1 com3 xxxx xxxx xxxx com4 xxxx xxxx xxxx 1/3duty lsb se g ment out p ut msb 123456789 37383940 com1 d8 d5 d2 d8 d5 d2 d8 d5 d2 d2 d8 d5 d2 com2 d7 d4 d1 d7 d4 d1 d7 d4 d1 d1 d7 d4 d1 com3 d6 d3 x d6 d3 x d6 d3 x x d6 d3 x com4 xxxxxxxxx xxxx 1/4duty lsb se g ment out p ut msb 123456789 37383940 com1 d8 d4 d8 d4 d8 d4 d8 d4 d8 d8 d4 d8 d4 com2 d7 d3 d7 d3 d7 d3 d7 d3 d7 d7 d3 d7 d3 com3 d6 d2 d6 d2 d6 d2 d6 d2 d6 d6 d2 d6 d2 com4 d5 d1 d5 d1 d5 d1 d5 d1 d5 d5 d1 d5 d1
fedl9480-01 ML9480 23/37 ? ram writing in 1/3 duty drive mode (when i2c pin is "h" and mode pin is "h") 1/3dutystandard ram fillin g lsb se g ment out p ut msb 123456789??? com1 a8 a5 a2 8 b5 b2 c8 c5 c2 ??? com2 a7 a4 a1 7 b4 b1 c7 c4 c1 ??? com3 a6 a3 x 6 b3 x c6 c3 x ??? com4 xxxxxxxxx??? 1/3dutyentire ram fillin g by rewritin g lsb se g ment out p ut msb 123456789 com1 a8 a5 a2/b8 b5 b2/c8 c5 c2/d8 d5 d2/e8 com2 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 com3 a6 a3 b6 b3 c6 c3 d6 d3 e6 com4 xxxxxxxxx
fedl9480-01 ML9480 24/37 v lcd gnd v lcd gnd v lcd /2 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd v lcd /2 ? common waveforms a t 1/2-bias com4 com1 com2 com4 com3 com1 com2 com1 com3 com3 com1 com3 com2 com4 com2 com4 com1 4 (1) at static (2) at 1/2-duty a t 1/3-bias (3) at 1/3-duty (4) at 1/4-duty
fedl9480-01 ML9480 25/37 common and segment output waveforms ? at static display example on com1 off com1 com2 com3 com4 seg2 seg3 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9480-01 ML9480 26/37 common and segment output waveforms - ? at 1/2 duty 1/2bias display example com1 on com2 of f seg2 seg3 com1 com3 com2 com4 seg1 s e g 1 s e g 2 s e g 3 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2
fedl9480-01 ML9480 27/37 common and segment output waveforms ?at 1/2 duty1/3bias display example com1 on com2 of f seg2 seg3 com1 com3 com2 com4 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9480-01 ML9480 28/37 ? common and segment output waveforms ? at 1/3-duty display example com1 on com2 of f com3 seg com1 com2 com4 com3 seg1 seg2 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9480-01 ML9480 29/37 ? common and segment output waveforms ? at 1/4-duty display example com1 com2 on com3 off com4 seg2 seg3 com4 com1 com2 com3 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9480-01 ML9480 30/37 power on sequence power off sequence any state display off wait 30ms v dd power off vlcd power off or vdd, vlcd power off at one time start vdd power on or vdd, vlcd power on at one time v lcd power on clock input when an external clock input mode any command
fedl9480-01 ML9480 31/37 example of application circuit cascade configuration 1 serial in terface internal cr oscillator circuit used 1/4duty resetb pin + external capacitance connection to configure poc circuit the common outputs of the slave chip output gnd-level. so com1 to com4 set to open. [external component] cp = 0.1 [f] (bypass capacitor between power supplies) crst = 4.7 [f] (capacitance for external poc circuit) m/s vlcd bias duty0 duty1 i2c load clock sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg40 com2 com3 com4 cko data ML9480 master) gnd m/s vlcd bias duty0 duty1 i2c load clock sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg40 com2 com3 com4 cko data ML9480 (slave) gnd 5v 5v 5v 5v open open open open open open cpu liquid crystal panel 1/4duty 40 n segments open cp cp cp cp crst crst poceb poceb sa1 sa1 mode mode
fedl9480-01 ML9480 32/37 cascade configuration 2 ii 2 c interface external rf-based cr oscillator circuit used 1/4duty external resetb signal input the common outputs of the slave chip output gnd-level. so com1 to com4 set to open. [external component] cp = 0.1 [f] (bypass capacitor between power supplies), rf = 470 [k ? ] (external r, resistor for cr oscillator circuit), rup = resistor for sda data bus pull-up m/s vlcd bias duty0 duty1 i2c load scl sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg40 com2 com3 com4 cko sda ML9480 master) gnd m/s vlcd bias duty0 duty1 i2c load scl sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg40 com2 com3 com4 cko sda ML9480 (slave) gnd 5v 5v open open open open cpu liquid crystal panel1/4duty 40 n open rf 5v 5v 5v cp cp cp cp poceb rup poceb sa1 sa1 mode mode
fedl9480-01 ML9480 33/37 pad configuration pad layout (pattern face) c hip size : 3.30 mm 0.90mm chip thickness : 400 ? m 20 ? m minimum bump pitch : 50 ? m bump height : 15 ? m 3 ? m 94 39 1 38 y x b a ( 0,0) bump and alignment mark dimensions (pattern face) p ad no.1 ? 38 : 32 ? m x 80 ? m pad no.39 ? 94 : 30 ? m x 84 ? m alignment marks a and b : see below [mark a] [mark b] alignment mark x-coordinate ( ? m) y-coordinate ( ? m) mark a 1506 -190 mark b -1539 309 aluminum (top metal) passivation 30 ? m 30 ? m 30 ? m 30 ? m 30 ? m 30 ? m aluminum (top metal) passivation 47 ? m 55 ? m 47 ? m 55 ? m coordinate position coordinate position
fedl9480-01 ML9480 34/37 pad center coordinates pad number pad name x-coordinate (? m) y-coordinate (? m) pad number pad name x-coordinate (? m) y-coordinate (? m) 1 dummy -1430 -308 41 com2 1325 309 2 gndo -1350 -308 42 com3 1275 309 3 duty1 -1270 -308 43 com4 1225 309 4 duty0 -1190 -308 44 dummy 1175 309 5 a0 -1110 -308 45 seg1 1125 309 6 a1 -1030 -308 46 seg2 1075 309 7 sa0 -950 -308 47 seg3 1025 309 8 sa1 -870 -308 48 seg4 975 309 9 vddo -790 -308 49 seg5 925 309 10 sdaack -710 -308 50 seg6 875 309 11 data(sda) -630 -308 51 seg7 825 309 12 clock(scl) -550 -308 52 seg8 775 309 13 load -470 -308 53 seg9 725 309 14 vdd -390 -308 54 seg10 675 309 15 vdd -310 -308 55 seg11 625 309 16 vdd -230 -308 56 seg12 575 309 17 gnd -150 -308 57 seg13 525 309 18 gnd -70 -308 58 seg14 475 309 19 gnd 10 -308 59 seg15 425 309 20 vlcd 90 -308 60 seg16 375 309 21 vlcd 170 -308 61 seg17 325 309 22 vlcd 250 -308 62 seg18 275 309 23 resetb 330 -308 63 seg19 225 309 24 osc1 410 -308 64 seg20 175 309 25 osc2 490 -308 65 com1 125 309 26 oscr 570 -308 66 com2 75 309 27 cko 650 -308 67 com3 25 309 28 syncb 730 -308 68 com4 -25 309 29 vddo 810 -308 69 seg21 -75 309 30 i2c 890 -308 70 seg22 -125 309 31 mode 970 -308 71 seg23 -175 309 32 m/s 1050 -308 72 seg24 -225 309 33 poceb 1130 -308 73 seg25 -275 309 34 osci/e 1210 -308 74 seg26 -325 309 35 bias 1290 -308 75 seg27 -375 309 36 test1 1370 -308 76 seg28 -425 309 37 gndo 1450 -308 77 seg29 -475 309 38 dummy 1530 -308 78 seg30 -525 309 39 dummy 1425 309 79 seg31 -575 309 40 com1 1375 309 80 seg32 -625 309
fedl9480-01 ML9480 35/37 pad number pad name x-coordinate (? m) y-coordinate (? m) pad number pad name x-coordinate (? m) y-coordinate (? m) 81 seg33 -675 309 82 seg34 -725 309 83 seg35 -775 309 84 seg36 -825 309 85 seg37 -875 309 86 seg38 -925 309 87 seg39 -975 309 88 seg40 -1025 309 89 dummy -1075 309 90 com4 -1125 309 91 com3 -1175 309 92 com2 -1225 309 93 com1 -1275 309 94 dummy -1325 309
fedl9480-01 ML9480 36/37 revision history page document no. issue date previous edition new edition description fedl9480-01 oct .1,2012 ? ? final edition 1 issued
fedl9480-01 ML9480 37/37 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsib ility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human in jury (such as a medical instrument, transportation equipment, aerospace machinery, nucl ear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for an y such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2012 lapis semiconductor co., ltd.

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